In an integrated circuit, different power-source voltages may be applied intentionally to an external power-source.terminal and to an internal circuit thereof with a view to improving the characteristics of the integrated circuit. However, as a higher-speed integrated circuit with a smaller feature size has been implemented, parasitic are produced therein so that different power-source voltages are applied unintentionally to the external power-source terminal and to the internal circuit.
The following are two conventional embodiments in which different power-source voltages are applied intentionally and unintentionally.
To reduce the power consumption of an integrated circuit or increase the operating speed thereof, a power-source voltage applied to an internal circuit block may be used selectively. For example, a circuit block which should be reduced in power consumption is supplied with a voltage lower than a power-source voltage applied to a power-source terminal, while another circuit block which should operate at a higher speed is supplied with the power-source voltage equal to the external power-source voltage. In thus designing the integrated circuit, it is necessary to create a gate-level delay library for each of the power-source voltages and selectively use a desired delay library in order to verify a delay in signal propagation for the integrated circuit and the operation thereof.
When a consumed current flows through a power-source line (hereinafter referred to as a VDD line) for supplying a power-source potential to a circuit block in an integrated circuit and through a ground line (hereinafter referred to as a VSS line) for supplying a ground potential, a wiring parasitic composed of resistance (R), capacitance (C), and inductance (L) emerges at the VDD or VSS line and causes a voltage variation. For the sake of simplicity, it is assumed here that the parasitic on the power-source line is composed only of, e.g., resistance. Since the power-source voltage effectively applied to the circuit block is reduced by the voltage variation resulting from the wiring resistance, a delay time is increased accordingly. However, a conventional method of calculating a delay is disadvantageous in that the error between the result of analysis and the result of measurement is increased because of postulated ideal VDD and VSS lines which undergo no variation in power-source voltage applied thereto.
To prevent the error from being increased, e.g., Japanese Laid-Open Patent Publication HEI 6-124318 has disclosed a simulation method wherein the resistance of a power-source line is calculated by a data extracting unit, a process-parameter storing unit, and a power-source-voltage storing unit, while a drain current in a MOSFET as a gate element is calculated by a gain-coefficient calculating unit and a drain-current calculating unit. After a voltage drop on the power-source line is calculated by using the resistance on the power-source line and the drain current, a delay time is calculated by a propagation delay calculator from the gain coefficient xcex2 of the drain current and an incidental capacitance.
As mentioned above, since the delay-data extracting process of obtaining desired delay data from the cell library is based on the setting of the power-source voltage at a specified value, it is necessary to repeatedly extract delay data a number of times equal to the number of different power-source voltages. With a multi-input gate such as a multi-bit adder cell, extraction time is elongated and hence the time required to design a cell library is elongated disadvantageously. In addition, a power-source voltage in consideration of an optimum delay time has been incompatible with a power-source voltage in consideration of optimum power consumption.
Japanese Laid-Open Patent Publication HEI 6-124318 shown in the second conventional embodiment has not disclosed the relationship between the gain coefficient xcex2 and the delay time in the propagation delay calculator, which is an important factor in calculating the dependency of the delay time on the power-source voltage and has not shown a specific method of calculating a delay time.
To analyze the delay time based on the dependency of the gain coefficient xcex2 on the power-source voltage, there has been proposed a method of calculating the time required to charge or discharge a load capacitance or load resistance based on the voltage-dependency of a drain current in a MOSFET by a transistor-level or switch-level circuit simulation. However, the method is not practical since it uses a transistor-level netlist containing an increased number of circuit components as the target of the circuit simulation and therefore considerably long time is required by a large-scale circuit.
To calculate the dependency of the delay time on the power-source voltage, there has been proposed a method of multiplying the delay time by a coefficient indicative of the dependency of the delay time on the power-source voltage, which has been calculated previously. There has also been proposed a method of calculating a plurality of effective power-source voltages from which potentials corresponding to variations in power-source voltage on the VDD and VSS lines have preliminarily been reduced under each of the operating conditions and using the delay values extracted for the respective power-source voltages, as described in the first conventional embodiment. In the foregoing.methods, however, the effective power-source voltages should be predetermined and it is impossible to reliably analyze the influence of voltage variations on different power-source lines produced in each of the circuit blocks in an actual integrated circuit, including a plurality of circuit blocks connected to power-source lines at different voltages and circuit blocks operating at different frequencies.
With an integrated circuit having internal circuit blocks operating at different power-source voltages, as used in the first conventional embodiment, a delay for the whole integrated circuit cannot be calculated by the method in which the coefficient indicative of the dependency of the delay time on the power-source voltage is used as a multiplier factor without distinction.
It is therefore an object of the present invention to reliably calculate a delay time for a logic circuit by easily and analytically calculating the dependency of the delay time on a power-source voltage and thereby thoroughly overcome the foregoing conventional problems.
To attain the foregoing object, the present invention multiplies a delay time for a logic circuit to which a first power-source voltage is applied by a power-source voltage coefficient which is a ratio of a second power-source voltage to the first power-source voltage and by a ratio of a drain saturation current in a FET when the first power-source voltage is applied thereto to a drain saturation current in the FET when the second power-source voltage is applied thereto and thereby calculates a delay time for the logic circuit to which the second power-source voltage is applied.
A first method of calculating a delay in signal propagation time for a logic circuit composed of a plurality of logic elements each including a FET, the delay in signal propagation time for said logic circuit resulting from first and second power-source voltages being applied to the logic circuit, the method comprising the steps of: designating, as a power-source voltage coefficient, a ratio of the second power-source voltage to the first power-source voltage; designating, as a current coefficient, a ratio of a drain saturation current in the FET when the first power-source voltage is applied thereto to a drain saturation current in the FET when the second power-source voltage is applied thereto; calculating a first delay time, the first delay time being a delay time for the logic circuit when the first power-source voltage is applied thereto; calculating a product of the first delay time, the power-source voltage coefficient, and said current coefficient; and designating the result of the product as a second delay time which is a delay time for the logic circuit when the second power-source voltage is applied thereto.
In accordance with the first method of calculating a delay for a logic circuit, once the relationship between the power-source voltage and the drain saturation current in the FET is defined, the dependency of the delay time for the logic circuit on the power-source voltage can be calculated easily and analytically by using delay data extracted at the first power-source voltage from a cell library.
A second method of calculating a delay for a logic circuit according to the present invention is a method of calculating a delay in signal propagation time for a logic circuit composed of a plurality of circuit blocks resulting from different effective power-source voltages at which the circuit blocks operate, each of the circuit blocks being composed of a plurality of logic elements each including a FET, the method comprising the.steps of: calculating a power-source voltage coefficient which is a ratio of the power-source voltage for each of the circuit blocks to a reference power-source voltage; calculating a current coefficient which is a ratio of a drain saturation current in the FET when the reference power-source voltage is applied thereto to a drain saturation current in the,FET when the effective power-source voltage for each of the circuit blocks is applied thereto; and calculating a reference delay time, the reference delay time being a delay time for each of the circuit blocks when the reference power-source voltage is applied thereto; calculating a product of the reference delay time, the power-source voltage coefficient for each of the circuit blocks, and the current coefficient for each of the circuit blocks; and designating the result of the product as an effective delay time which is a delay time for each of the circuit blocks.
In accordance with the second method of calculating a delay for a logic circuit, once the relationship between the power-source voltage and the drain saturation current in the FET is defined for each circuit block, the dependency of the delay time on the power-source voltage for each of the plurality of circuit blocks of the logic circuit can be calculated easily and analytically by using the delay data extracted at the reference power-source voltage from the cell library.
A third method of calculating a delay for a logic circuit according to the present invention is a method of calculating, a delay in signal propagation time for a logic circuit composed of a plurality of logic elements each including a FET, the delay in signal propagation time for the logic circuit resulting from a variation in power-source voltage, the method comprising the steps of: calculating a voltage variation caused by a current consumed by the logic circuit and by a wiring parasitic on a power-source line and calculating a difference between a reference power-source voltage applied to a power-source terminal and the voltage variation to calculate an effective power-source voltage applied to the logic circuit; calculating a power-source voltage coefficient which is a ratio of the effective power-source voltage to the reference power-source voltage, while calculating a current coefficient which is a ratio of a drain saturation current in the FET when the reference power-source voltage is applied thereto to a drain saturation current in the FET when the effective power-source voltage is applied thereto; and calculating a reference delay time, the reference delay time being a delay time for the logic circuit when the reference power-source voltage is applied thereto using the reference delay time data; calculating a product of the reference delay time, the power-source voltage coefficient for the logic circuit, and the current coefficient for the logic circuit; and determining the result of the product as an effective delay time which is a delay time for the logic circuit when the effective power-source voltage is applied thereto.
In accordance with the third method of calculating a delay for a logic circuit, once the relationship between the effective power-source voltage in which the voltage variation is reflected and the drain saturation current in the FET is defined, the dependency of the delay time for the logic circuit on the power-source voltage when the effective power-source voltage is applied can be calculated easily and analytically by using the delay data extracted at the reference power-source voltage from the cell library.
In the third method of calculating a delay for a logic circuit, the current consumed by the logic circuit is preferably a sum of currents consumed by specified ones of the plurality of logic elements operating simultaneously at a given operating time and a voltage variation on a power-source line connected to the specified logic elements is preferably calculated based on the sum of the consumed currents to provide the voltage variation. This enables easy and analytical calculation of the delay time in consideration of a dynamic voltage variation on the power-source line resulting from the time-varying consumed current.
In the first to third methods of calculating a delay for a logic circuit, the FET is preferably a P-channel MOSFET. With the arrangement, since the dependency of the drain saturation current on the power-source voltage is higher in the P-channel MOSFET than in an N-channel MOSFET, the dependency of the delay time on the power-source voltage is substantially proportional to the ratio of the power-source voltage to the drain saturation current, so that the dependency of the delay time on the power-source voltage when the power-source voltage is applied is reliably calculated.
In the first to third methods of calculating a delay for a logic circuit, the drain saturation current in the FET is preferably calculated by raising a difference between the power-source voltage and a threshold voltage of the FET to the power of a specified coefficient and multiplying the resulting value by a current gain coefficient. This enables reliable calculation of the drain saturation current in the FET.
A first apparatus for calculating a delay for a logic circuit is an apparatus for calculating, in simulating a logic circuit composed of a plurality of logic elements each including a FET, a delay in signal propagation time for the logic circuit resulting from a power-source voltage supplied thereto, the apparatus comprising: layout-data supplying means for supplying layout data used to determine the placement of the logic elements in the logic circuit; netlist supplying means for supplying netlist for the logic circuit: process parameter supplying means for supplying process information used to determine the routing of the logic circuit and electric characteristics of the logic elements; library-data supplying means for supplying delay data for the logic elements; delay-power source-coefficient determining means for determining a power-source voltage coefficient which is a ratio of a second power-source voltage to a first power-source voltage, while determining a current coefficient which is a ratio of a drain saturation current in the FET when the first power-source voltage is applied thereto to a drain saturation current in the FET when the second power-source voltage is applied thereto; delay calculating means for calculating a delay time for the logic circuit when the first power-source voltage is applied thereto based on the delay data, the layout data, the process information, and the netlist; and effective-delay calculating means for calculating a product of the delay time calculated by the delay calculating means, the power-source voltage coefficient, and the current coefficient and designating the result of calculation as an effective delay time for the logic circuit when the second power-source voltage is applied thereto.
In the first apparatus for calculating a delay for a logic circuit, once the relationship between the power-source voltage and the drain saturation current is defined, the dependency of the delay time for the logic circuit on the power-source voltage can be calculated easily and analytically by using the delay data extracted at the first power-source voltage from the cell library.
In the first apparatus for calculating a delay for a logic circuit, the logic circuit is preferably composed of a plurality of circuit blocks operating at different power-source voltages, the apparatus further comprising power-source-voltage-information supplying means for supplying power-source-voltage information for each of the logic circuit and the circuit blocks, the delay-power-source-coefficient determining means having means for determining block power-source voltage coefficients which define respective ratios of the power-source voltages for the individual circuit blocks to the reference power-source voltage and means for determining block current coefficients which define respective ratios of the drain saturation currents in the FETs when the reference power-source voltage is applied thereto to the drain saturation currents in the FETs when the power-source voltages for the individual circuit blocks are applied thereto. With the arrangement, once the relationship between the power-source voltage and the drain saturation current in the FET is defined for each circuit block, the dependency of the delay time for each of the plurality of circuit blocks of the logic circuit on the power-source voltage can be obtained easily and analytically by using the delay data extracted at the reference power-source voltage from the cell library.
A second apparatus for calculating a delay for a logic circuit according to the present invention is an apparatus for calculating, in simulating a logic circuit composed of a plurality of logic elements each including a FET, a delay in signal propagation time for the logic circuit resulting from a variation in power-source voltage supplied thereto, the apparatus comprising: layout-data supplying means for supplying layout data used to determine the placement of the logic elements in the logic circuit; netlist supplying means for supplying netlist for the logic circuit; process-parameter supplying means for supplying process information used to determine the routing of the logic circuit and electric characteristics of the logic elements; library-data supplying means for supplying delay data and consumed current data each for the logic elements; signal-wiring extracting means for extracting a wiring parasitic on a signal line by using the layout data and the process parameters; power-source-line-parasitic extracting means for extracting a wiring parasitic on a power-source line connected to a power-source terminal and to the logic circuit by using the layout data and the process parameters; consumed-current calculating means for calculating a current consumed by the logic circuit by using the wiring parasitic on the signal line and the consumed current data; effective-power-source-voltage calculating means for calculating a voltage variation on the power-source line by using the consumed current and the wiring parasitic on the power-source line and calculating a difference between a power-source voltage applied to the power-source terminal and the voltage variation to calculate an effective power-source voltage; delay-power-source-coefficient determining means for determining a power-source voltage coefficient which is a ratio of the effective power-source voltage to the power-source voltage, while determining a current coefficient which is a ratio of a drain saturation current in the FET when the power-source voltage is applied thereto to a drain saturation current in the FET when the-effective power-source voltage is applied thereto; delay calculating means for calculating a delay time when the power-source voltage is applied thereto by using the wiring parasitic on the signal line and the delay data for the logic elements; and effective-delay calculating means for calculating a product of the delay time calculated by the delay calculating means, the power-source voltage coefficient, and the current coefficient and designating the result of calculation as an effective delay time for the logic circuit.
In the second apparatus for calculating a delay for a logic circuit, once the relationship between the effective power-source voltage in which the voltage variation is reflected and the drain saturation current in the FET is defined, the dependency of the delay time for the logic circuit on the power-source voltage when the effective power-source voltage is applied thereto can be calculated easily and analytically by using the delay data extracted at the reference power-source voltage from the cell library.
In the second apparatus for calculating a delay for a logic circuit, the consumed-current calculating means preferably calculates a sum of respective currents consumed by specified ones of the plurality of logic elements operating simultaneously at a given operating time, the effective-power-source-voltage calculating means preferably calculates a voltage variation on a power-source line connected to the specified logic elements by using the sum of the consumed currents and the wiring parasitic on the power-source line, and the delay-power-source-coefficient determining means preferably calculates the power-source voltage coefficient and the current coefficient for each of the plurality of logic elements by using the effective power-source voltage applied to the logic element in order of temporal precedence of the operating times of the logic elements. This enables easy and analytical calculation of the delay time in consideration of a dynamic voltage variation on the power-source line resulting from the time-varying consumed current.
In the second apparatus for calculating a delay for a logic circuit, the logic circuit is preferably an integrated circuit composed of at least one circuit block having at least one standard cell, the integrated circuit is preferably provided with an external power-source terminal to which the power-source voltage is applied thereto, at least one circuit block is preferably provided with a block power-source terminal connected to the external power-source terminal to receive a voltage for driving the circuit block applied thereto, at least one standard cell is preferably provided with a cell power-source terminal connected to the block power-source terminal to receive a voltage for driving the standard cell applied thereto, the consumed current calculating means preferably has: block; level consumed current calculating means for calculating a current consumed by the circuit block by using the wiring parasitic on the signal line and the consumed current data for the standard cell; and chip-level-consumed-current calculating means for calculating a current consumed by the integrated circuit by using the current consumed by the circuit block, and the effective-power-source-voltage calculating means preferably has: chip-level-voltage-variation calculating means for calculating a chip-level voltage variation which is a voltage variation on the power-source line between the external power-source terminal and the block power-source terminal by using the current consumed by the circuit block; chip-level-effective-power-source-voltage calculating means for calculating a chip-level effective power-source voltage by calculating a difference between the power-source voltage applied to the external power-source terminal and the chip-level voltage variation; block-level-voltage-variation calculating means for calculating a block-level-voltage variation which is a voltage variation between the block power-source terminal and the cell power-source terminal based on the consumed current.data for the standard cell; and block-level-effective-power-source-voltage calculating means for calculating a block-level effective power-source voltage by calculating a difference between the chip-level-effective-power-source voltage and the block-level voltage variation, the apparatus calculating an effective delay time for the integrated circuit-based on the block-level effective power-source voltage. With the arrangement, the consumed currents and the effective power-source voltages are calculated hierarchically and sequentially on the chip level, on the block level, and on the cell level, so that the delay time is reliably calculated even in a large-scale integrated circuit.
In the second apparatus for calculating a delay for a logic circuit, the consumed-current calculating means preferably calculates a sum of respective currents consumed by specified ones of a plurality of standard cells operating simultaneously at a given operating time, designates the sum as a current consumed by the standard cells, and calculates a voltage variation on a power-source line connected to the specified standard cells by using the current consumed by the standard cells and the wiring parasitic on the power-source line and the delay-power-source-coefficient determining means preferably calculates the power-source voltage coefficient and the current coefficient for each of the plurality of standard cells by using the effective power-source voltage applied to the standard cell in order of temporal precedence of the operating times of the standard cells. This enables easy and analytical calculation of the delay time in consideration of a dynamic voltage variation on the power-source line resulting from the time-varying consumed current.
In the second apparatus for calculating a delay for a logic circuit, the consumed-current, calculating means preferably has switching-frequency-data supplying means for supplying a switching frequency at each node in the netlist and calculates the current consumed by the integrated circuit by using the switching frequency, the wiring parasitic, and the consumed current data for the standard cell. With the arrangement, the switching frequency is not dependent on the wiring parasitic or on the current data in the cell library, so that it is possible to calculate the switching frequency without information on the load capacitance and resistance capacitance of actual wiring. As a result, it is not necessary to resupply a test pattern and simulate again the consumed current even in the case where the manufacturing process is changed, where the operating conditions such as the operating frequency and power-source voltage are changed, or where the configuration of the layout is changed as in a soft macro library, resulting in a reduced number of process steps for developing an integrated circuit.
In the second apparatus for calculating a delay for a logic circuit, the consumed-current calculating means preferably calculates a transition probability which is the probability of one logic value making a transition to the other logic value by using a logic function contained in the netlist and calculates the current consumed by the integrated circuit by using the transition probability, the wiring parasitic, and the consumed current data for the standard cell. With the arrangement, it is not necessary to resupply a test pattern and simulate again the consumed current even in the case where the manufacturing process is changed, where the operating conditions such as the operating frequency and power-source voltage are changed, or where the configuration of the layout is changed as in a soft macro library, resulting in a reduced number process steps for developing an integrated circuit.
Preferably, the first or second apparatus for calculating a delay for a logic circuit further comprises convergence condition judging means for storing the result of calculation outputted from the effective-power-source-voltage calculating means, judging whether or not a difference between the result of calculation obtained immediately before from the effective power-source-voltage calculating means and the stored result of calculation falls within a specified range, and, if the difference does not fall in the specified range, causing the consumed current calculating means and the effective-power-source-voltage calculating means to repeat the same procedures till the difference falls within the specified range. With the arrangement, the current consumed by the circuit and the effective power-source voltage supplied thereto, which are greatly dependent on each other, are calculated by forming a recursive loop, so that the delay time is calculated with higher accuracy.
In the first or second apparatus for calculating a delay for a logic circuit, a drain saturation current in the FET is preferably calculated by raising a difference between a power-source voltage and a threshold voltage of the FET to the power of a specified coefficient-and multiplying the resulting value by a current gain coefficient. This enables reliable calculation of the drain saturation current in the FET.
A first method of calculating delay data for a delay library according to the present invention is a method of calculating delay data representing a delay in signal propagation time for a delay library to be used in simulating a logic circuit composed of logic elements each including a FET, comprising the steps of: defining a power-source voltage coefficient, the power-source voltage coefficient being a ratio of a second power-source voltage to a first power-source voltage; defining a current coefficient, the current coefficient being a ratio of a drain saturation current in the FET when the first power-source voltage is applied thereto to a drain saturation current in the FET when the second power-source voltage is applied thereto; defining a first delay time, the first delay time being a delay time for the logic circuit when the first power-source voltage is applied thereto; and calculating a product of the first delay time, the power-source voltage coefficient, and the current coefficient to determine a second delay time, the second delay time being a delay time for the logic circuit when the second power-source voltage is applied thereto and designating the second delay time as delay data.
In accordance, with the first method of calculating delay data for a delay library according to the present invention, once the relationship between the power-source voltage and the drain saturation current in the FET is defined, the dependency of the delay time for the logic circuit on the power-source voltage can be calculated easily and analytically by using the delay data extracted at the first power-source voltage from the cell library. This reduces time required to extract the delay data and thereby permits short-term development of the cell library.
A second method of calculating delay data for a delay library according to the present invention is a method of calculating delay data representing a delay in signal propagation time for a delay library to be used in simulating a logic circuit composed of logic circuits including a P-channel MOSFET and an N-channel MOSFET, the method comprising the steps of: defining a power-source voltage coefficient, the power-source voltage being a ratio of a second power-source voltage to a first power-source voltage; defining a first current coefficient, the first current coefficient being a ratio of a drain saturation current in the P-channel MOSFET when the first power-source voltage is applied thereto to a drain saturation current in the P-channel MOSFET when the second power-source voltage is applied thereto; defining a second current coefficient, the second current coefficient being a ratio of a drain saturation current in the N-channel MOSFET when the first power-source voltage is applied thereto to a drain saturation current in the N-channel MOSFET when the second power-source voltage is applied thereto; defining a first rise delay time and a first fall delay time each for the logic circuit when the first power-source voltage is applied thereto; calculating a product of the first rise delay time, the power-source voltage coefficient, and the first current coefficient to determine a second rise delay time, the second rise delay time being a rise delay time for the logic circuit when the second power-source voltage is applied thereto and designating the second rise delay time as rise delay data; and calculating a product of the first fall delay time, the power-source voltage coefficient, and the second current coefficient to determine a second fall delay time, the second fall delay time being a fall delay time for the logic circuit when the second power-source voltage is applied thereto and designating the second fall delay time as fall delay data.
The second method of calculating delay data for a delay library achieves the same effect as achieved by the first method of calculating delay data for a delay library. In addition to that, the second method determines, as a rise delay produced in driving the P-channel MOSFET, the second rise delay time which is the rise delay time for the logic circuit when the second power-source voltage is applied thereto, while determining, as a fall delay produced in driving the N-channel MOSFET, the second fall delay time which is the fall delay time for the logic circuit when the second power-source voltage is applied. As a consequence, the rise delay data and the fall delay data can be calculated individually to compose the delay data. The resulting delay library is more specific and higher in accuracy.
To further attain the foregoing objects, the present invention may further comprise a storage element storing a computer readable program for calculating a delay in signal propagation time for a logic circuit composed of a plurality of logic elements each including a FET, the delay in signal propagation time for the logic circuit resulting from first and second power-source voltages being applied to the logic circuit, the program directing a computer to execute the steps of: designating, as a power-source voltage coefficient, a ratio of the second power-source voltage to the first power-source voltage; designating, as a current coefficient, a ratio of a drain saturation current in the FET when the first power-source voltage is applied thereto to a drain saturation current in the FET when the second power-source voltage is applied thereto; calculating a first delay time, the first delay time being a delay time for the logic circuit when the first power-source voltage is applied thereto; calculating a product of the first delay time, the power-source voltage coefficient, and the current coefficient; and designating the result of the product as a second delay time which is a delay time for the logic circuit when the second power-source voltage is applied thereto.
In accordance with the storage element, once the relationship between the power-source voltage and the drain saturation current in the FET is defined, the dependency of the delay time for the logic circuit on the power-source voltage can be calculated easily and analytically by using delay data extracted at the first power-source voltage from a cell library.
To further attain the foregoing objects, the present invention may further comprise an alternative storage element storing a computer readable program for calculating a delay in signal propagation time for a logic circuit composed of a plurality of circuit blocks resulting from different effective power-source voltages at which the circuit blocks operate, each of the circuit blocks being composed of a plurality of logic elements each including a FET, the program directing a computer to execute the steps of: calculating a power-source voltage coefficient which is a ratio of the power-source voltage for each of the circuit blocks to a reference power-source voltage; calculating a current coefficient which is a ratio of a drain saturation current in the FET when the reference power-source voltage is applied thereto to a drain saturation current in the FET when the effective power-source voltage for each of the circuit blocks is applied thereto; and calculating a reference delay time, the reference delay time being a delay time for each of the circuit blocks when the reference power-source voltage is applied thereto; calculating a product of the reference delay time, the power-source voltage coefficient for each of the circuit blocks, and the current coefficient for each of the circuit blocks; and designating the result of the product as an effective delay time which is a delay time for each of the circuit blocks.
In accordance with the alternative storage element, once the relationship between the power-source voltage and the drain saturation current in the FET is defined for each circuit block, the dependency of the delay time on the power-source voltage for each of the plurality of circuit blocks of the logic circuit can be calculated easily and analytically by using the delay data extracted at the reference power-source voltage from the cell library.
To further attain the foregoing objects, the present invention may further comprise another alternative storage element storing a computer readable program for calculating a delay in signal propagation time for a logic circuit composed of a plurality of logic elements each including a FET, the delay in signal propagation time for the logic circuit resulting from a variation in power-source voltage, the program directing a computer to execute the steps of: calculating a voltage variation caused by a current consumed by the logic circuit and by a wiring parasitic on a power-source line and calculating a difference between a reference power-source voltage applied to a power-source terminal and the voltage variation to calculate an effective power-source voltage applied to the logic circuit; calculating a power-source voltage coefficient which is a ratio of the effective power-source voltage to the reference power-source voltage, while calculating a current coefficient which is a ratio of a drain saturation current in the FET when the reference power-source voltage is applied thereto to a drain saturation current in the FET when the effective power-source voltage is applied thereto; and calculating a reference delay time, the reference delay time being a delay time for the logic circuit when the reference power-source voltage is applied thereto using the reference delay time data; calculating a product of the reference delay time, the power-source voltage coefficient for the logic circuit, and the current coefficient for the logic circuit; and determining the result of the product as an effective delay time which is a delay time for the logic circuit when the effective power-source voltage is applied thereto.
In accordance with the another alternative storage element, once the relationship between the effective power-source voltage in which the voltage variation is reflected and the drain saturation current in the FET is defined, the dependency of the delay time for the logic circuit on the power-source voltage when the effective power-source voltage is applied can be calculated easily and analytically by using the delay data extracted at the reference power-source voltage from the cell library.
In the above storage elements, the FET is preferably a P-channel MOSFET. With the arrangement, since the dependency of the drain saturation current on the power-source voltage is higher in the P-channel MOSFET than in an N-channel MOSFET, the dependency of the delay time on the power-source voltage is substantially proportional to the ratio of the power-source voltage to the drain saturation current, so that the dependency of the delay time on the power-source voltage when the power-source voltage is applied is reliably calculated.
In the above storage elements, the drain saturation current in the FET is preferably calculated by raising a difference between the power-source voltage and a threshold voltage of the FET to the power of a specified coefficient and multiplying the resulting value by a current gain coefficient. This enables reliable calculation of the drain saturation current in the FET.